Altera and Synopsys Partner to Create ASIC-like Design Solutions for System-On-Programmable-Chip Applications

Altera to support .lib, SDC and SDF standard formats for next-generation PLD devices

SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 14, 2001-- Altera Corporation (Nasdaq:ALTR - news) and Synopsys, Inc. (Nasdaq:SNPS - news) today announced a partnership to jointly create ASIC-like design solutions for system-on-programmable-chip (SOPC) devices to meet the need for next-generation design and verification flows for high-density programmable logic devices (PLDs). Designers will benefit from the application of technology such as .lib, SDC and SDF industry standards to increase the performance and flexibility of PLD design and verification flows.

"In response to the evolving complexity of SOPC solutions, Altera is working to provide customers with a more comprehensive design environment to maximize the power and performance of our programmable logic devices," said Erik Cleage, senior vice president of marketing at Altera. "This partnership with an industry-leader such as Synopsys confirms our commitment to provide our customers with best of breed technology, products, and services."

"We see our mutual customers targeting increasingly complex applications in Altera SOPC solutions," said Sanjiv Kaul, senior vice president and general manager of the physical synthesis business unit at Synopsys. "By leveraging our strength in ASIC design and verification, we provide our mutual customers with the power they need to take full advantage of Altera's high-performance programmable logic devices and win in the marketplace."

Synopsys and Altera are collaborating closely to develop next generation design flows. With the use of the .lib and SDC standards, Altera and Synopsys are able to leverage ASIC techniques for bringing performance and productivity to complex, high-density PLD design. For example, a wide variety of design constraints can be used to control the synthesis process to achieve the desired clock speed and area in a PLD. Synopsys makes available the SDC constraint format, which allows Altera's customers to use the same constraints for PLD designs as used in high-density ASIC synthesis. The same SDC constraints are then applied in place and route, saving time and bringing yet more control to the flow. This arms designers with more influence over the final implementation without getting caught in recode-and-reverify loops.

Building on the .lib, SDC, and SDF standards also allows the two companies to deliver a design flow that automatically works with proven verification tools such as PrimeTime® static timing analysis and VCS(TM) high-performance Verilog simulator. These flows are certified for use in verifying designs targeting Altera's high-density PLDs. Formality® formal verification, Scirocco(TM) VHDL simulation and LEDA® Checker RTL rule-checking tools will be added to the PrimeTime® and VCS flow to create a time-saving alternative to debugging a large PLD.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS - news), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

About Altera

Altera Corporation, The Programmable Solutions Company® , was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high-performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at http://www.altera.com.

Note to Editors: Synopsys, PrimeTime, Formality and LEDA are registered trademarks of Synopsys Inc. VCS, Scirocco and FPGA Compiler II are trademarks of Synopsys, Inc. Altera, The Programmable Solutions Company and the stylized Altera logo are trademarks of Altera Corporation in the U.S. and other countries. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

     Synopsys Inc., Mountain View
     Heather Kettmann, 650/584-4723
     kettmann@synopsys.com
         or
     Altera Corporation
     Bruce Fienberg, 408/544-6866
     bfienber@altera.com
        or
     Edelman Public Relations
     Stephanie Huang, 650/429-2762
     stephanie.huang@edelman.com